Microelectronic devices generally have a semiconductor die (i.e., a chip) that includes integrated circuitry with a high density of very small components. Typically, dies include an array of very small bond pads electrically coupled to the integrated circuitry. The bond pads are external electrical contacts through which the supply voltage, signals, etc., are transmitted to and from the integrated circuitry. After dies are formed, they are “packaged” to couple the bond pads to a larger array of electrical terminals that can be more easily coupled to the various power supply lines, signal lines, and ground lines. Conventional processes for packaging dies include electrically coupling the bond pads on the dies to an array of leads, ball pads, or other types of electrical terminals of an interposer substrate. The dies are then encapsulated to protect them from environmental factors (e.g., moisture, particulates, static electricity, and physical impact).
Different types of semiconductor dies may have widely different bond pad arrangements and yet should be compatible with similar external devices. Accordingly, existing packaging techniques can include attaching a redistribution layer to a semiconductor die. The redistribution layer includes lines and/or vias that connect the bond pads of the die with bond pads of the redistribution layer. The redistribution layer includes an array of leads, ball-pads, or other types of electrical terminals arranged to mate with the electrical terminals of external devices.
One challenge is that electromagnetic interference can impair the operation of high-performance semiconductor devices. As a result, it may be desirable to shield the integrated circuitry of a semiconductor die from electromagnetic interference. However, pre-formed copper lids and other forms of external shielding are costly and can be impractical. Similarly, pre-formed copper shields that are fully embedded within an encapsulant are also costly to incorporate into the packaging of semiconductor devices.
For ease of reference, throughout this disclosure identical reference numbers are used to identify similar or analogous components or features, but the use of the same reference number does not imply that the parts should be construed to be identical. Indeed, in many examples described herein, the identically-numbered parts are distinct in structure and/or function. Furthermore, the same shading may be used to indicate materials in a cross section that can be compositionally similar, but the use of the same shading does not imply that the materials should be construed to be identical.
Additionally, in the following description numerous specific details are discussed to provide a thorough and enabling description for embodiments of the present technology. One skilled in the relevant art, however, will recognize that the disclosure can be practiced without one or more of the specific details. In other instances, well-known structures or operations often associated with semiconductor devices are not shown, or are not described in detail, to avoid obscuring other aspects of the technology. In general, it should be understood that various other devices, systems, and methods in addition to those specific embodiments disclosed herein may be within the scope of the present technology.
As used herein, the terms “vertical,” “lateral,” “upper,” and “lower” can refer to relative directions or positions of features in the semiconductor die assemblies in view of the orientation shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down, and left/right can be interchanged depending on the orientation.